Key Features
- Explore the SpringCore RISC-V DSP architecture and its custom ISA extensions
- Understand an 8-stage pipelined processor with Harvard memory and interrupt handling
- Examine the software ecosystem, including LLVM, Eclipse IDE, and OpenOCD debugging
Who this book is for
This book is for computer architects, embedded systems engineers, DSP engineers, and RTL/FPGA designers interested in RISC-V processor implementation. It is also suitable for graduate students and researchers in computer architecture, VLSI, and SoC design who want to explore the SpringCore DSP architecture and its implementation. Familiarity with digital logic and processor architecture will help readers get the most from this book.